From b72b5d95286a2290554399e0803d4ba5e7b87f8d Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 4 Jul 2019 21:08:17 +0300 Subject: arch/x86: Clean up PIRQ_ROUTE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This code is currently only used by via/epia-m850, it is also somewhat buggy. Change-Id: I140e15d584d3f60f7824bcb71ce63724c11e3f46 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34078 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/arch/x86/Kconfig | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'src/arch/x86/Kconfig') diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 06aadedae6..631d981e45 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -329,3 +329,19 @@ config HAVE_CF9_RESET config HAVE_CF9_RESET_PREPARE bool depends on HAVE_CF9_RESET + +config PIRQ_ROUTE + bool + default n + +config MAX_PIRQ_LINKS + int + default 4 + depends on PIRQ_ROUTE + help + This variable specifies the number of PIRQ interrupt links which are + routable. On most chipsets, this is 4, INTA through INTD. Some + chipsets offer more than four links, commonly up to INTH. They may + also have a separate link for ATA or IOAPIC interrupts. When the PIRQ + table specifies links greater than 4, pirq_route_irqs will not + function properly, unless this variable is correctly set. -- cgit v1.2.3