From f47f5fb4f138d234ac0ea62a2420873afa8b86dc Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Tue, 22 Sep 2015 15:53:32 -0700 Subject: RISCV: modify arch_prog_run to handle payloads correctly. Unlike the other stages, the payload requires virtual memory to be set up and also a privelege level change. Change-Id: Ibbe2a55f7719d917f121a53a17c6d90e6b2ab3d1 Signed-off-by: Ronald G. Minnich Reviewed-on: http://review.coreboot.org/11699 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/arch/riscv/boot.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'src/arch/riscv') diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index d07d825d96..ab4ae95a19 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -18,11 +18,19 @@ */ #include +#include +#include +#include void arch_prog_run(struct prog *prog) { - void (*doit)(void *); + void (*doit)(void *) = prog_entry(prog); - doit = prog_entry(prog); - doit(prog_entry_arg(prog)); + if (ENV_RAMSTAGE && prog_type(prog) == ASSET_PAYLOAD) { + initVirtualMemory(); + write_csr(mepc, doit); + asm volatile("eret"); + } else { + doit(prog_entry_arg(prog)); + } } -- cgit v1.2.3