From f3d8580cce06608685e1389f4863acf24c452278 Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Wed, 10 Oct 2018 14:22:49 +0200 Subject: arch/riscv: Don't set FPU state to "dirty" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Quoting from the RISC-V Privileged Architecture manual version 1.10, chapter 3.1.11: The FS and XS fields use the same status encoding as shown in Table 3.3, with the four possible status values being Off, Initial, Clean, and Dirty. Status FS Meaning XS Meaning 0 Off All off 1 Initial None dirty of clean, some on 2 Clean None dirty, some clean 3 Dirty Some dirty Change-Id: If0225044ed52215ce64ea979d120014e02d4ce37 Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/c/28987 Reviewed-by: Philipp Hug Reviewed-by: Patrick Georgi Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/arch/riscv/virtual_memory.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'src/arch/riscv') diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 0061847c01..2f13ecb398 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -40,11 +40,6 @@ static int delegate = 0 void mstatus_init(void) { - uintptr_t ms = 0; - - ms = INSERT_FIELD(ms, MSTATUS_FS, 3); - write_csr(mstatus, ms); - // clear any pending timer interrupts. clear_csr(mip, MIP_STIP | MIP_SSIP); -- cgit v1.2.3