From c01d0920bb75e0b2849c26421be0a3fac6bc6198 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Mon, 4 Nov 2019 16:32:01 +0100 Subject: arch/riscv: Rename `stages.c` to `romstage.c` It's only used for romstage and is incompatible to ramstages. The latter get `cbmem_top` passed as a third argument now. Also drop comments that don't apply to this file anymore. Change-Id: Ibabb022860f5d141ab35922f30e856da8473b529 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/36611 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/arch/riscv/Makefile.inc | 2 +- src/arch/riscv/romstage.c | 35 +++++++++++++++++++++++++++++++++++ src/arch/riscv/stages.c | 44 -------------------------------------------- 3 files changed, 36 insertions(+), 45 deletions(-) create mode 100644 src/arch/riscv/romstage.c delete mode 100644 src/arch/riscv/stages.c (limited to 'src/arch/riscv') diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 16f160e8db..003852324b 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -98,7 +98,7 @@ endif #CONFIG_ARCH_BOOTBLOCK_RISCV ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y) romstage-y += boot.c -romstage-y += stages.c +romstage-y += romstage.c romstage-y += misc.c romstage-$(ARCH_RISCV_PMP) += pmp.c romstage-y += smp.c diff --git a/src/arch/riscv/romstage.c b/src/arch/riscv/romstage.c new file mode 100644 index 0000000000..d5f5a43ce1 --- /dev/null +++ b/src/arch/riscv/romstage.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Entry points must be placed at the location the previous stage jumps + * to (the lowest address in the stage image). This is done by giving + * stage_entry() its own section in .text and placing it first in the + * linker script. + */ + +#include +#include +#include +#include + +void stage_entry(int hart_id, void *fdt) +{ + HLS()->hart_id = hart_id; + HLS()->fdt = fdt; + smp_pause(CONFIG_RISCV_WORKING_HARTID); + + main(); +} diff --git a/src/arch/riscv/stages.c b/src/arch/riscv/stages.c deleted file mode 100644 index 5b27508c47..0000000000 --- a/src/arch/riscv/stages.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * This file contains entry/exit functions for each stage during coreboot - * execution (bootblock entry and ramstage exit will depend on external - * loading). - * - * Entry points must be placed at the location the previous stage jumps - * to (the lowest address in the stage image). This is done by giving - * stage_entry() its own section in .text and placing it first in the - * linker script. - */ - -#include -#include -#include -#include - -void stage_entry(int hart_id, void *fdt) -{ - /* - * Save the FDT pointer before entering ramstage, because mscratch - * might be overwritten in the trap handler, and there is code in - * ramstage that generates misaligned access faults. - */ - HLS()->hart_id = hart_id; - HLS()->fdt = fdt; - smp_pause(CONFIG_RISCV_WORKING_HARTID); - - main(); -} -- cgit v1.2.3