From 387417be03f9dcf9fe48fedd2e6ba6d356f51210 Mon Sep 17 00:00:00 2001 From: Xiang Wang Date: Mon, 9 Jul 2018 11:54:09 +0800 Subject: riscv: add support to check ISA extension MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support to check ISA extension for RISC-V. Change-Id: I5982fb32ed1dd435059edc6aa0373bffa899e160 Signed-off-by: Xiang Wang Reviewed-on: https://review.coreboot.org/27410 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer Reviewed-by: Philipp Hug --- src/arch/riscv/include/arch/cpu.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/arch/riscv') diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h index a0ca3ce534..6008c75122 100644 --- a/src/arch/riscv/include/arch/cpu.h +++ b/src/arch/riscv/include/arch/cpu.h @@ -16,6 +16,8 @@ #ifndef __ARCH_CPU_H__ #define __ARCH_CPU_H__ +#include + #define asmlinkage #if !defined(__PRE_RAM__) @@ -44,5 +46,10 @@ struct cpuinfo_riscv { #endif +static inline int supports_extension(char ext) +{ + return read_csr(misa) & (1 << (ext - 'A')); +} + struct cpu_info *cpu_info(void); #endif /* __ARCH_CPU_H__ */ -- cgit v1.2.3