From d9307c2e8aa3272fe57a67d2a5f31e38fa69d328 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Mon, 12 Dec 2016 15:09:42 -0800 Subject: riscv: Add support for timer interrupts MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit RISCV requires that timer interrupts be handled in machine mode and delegated as necessary. Also you can only reset the timer interrupt by writing to mtimecmp. Further, you must write a number > mtime, not just != mtime. This rather clumsy situation requires that we write some value into the future into mtimecmp lest we never be able to leave machine mode as the interrupt either is not cleared or instantly reoccurs. This current code is tested and works for harvey (Plan 9) timer interrupts. Change-Id: I8538d5fd8d80d9347773c638f5cbf0da18dc1cae Signed-off-by: Ronald G. Minnich Reviewed-on: https://review.coreboot.org/17807 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer --- src/arch/riscv/virtual_memory.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'src/arch/riscv/virtual_memory.c') diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 26a0169335..aceb72eebd 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -292,12 +292,21 @@ void initVirtualMemory(void) { void mstatus_init(void) { uintptr_t ms = 0; + ms = INSERT_FIELD(ms, MSTATUS_FS, 3); ms = INSERT_FIELD(ms, MSTATUS_XS, 3); write_csr(mstatus, ms); - clear_csr(mip, MIP_MSIP); - set_csr(mie, MIP_MSIP); + // clear any pending timer interrupts. + clear_csr(mip, MIP_STIP | MIP_SSIP); + + // enable machine and supervisor timer and + // all other supervisor interrupts. + set_csr(mie, MIP_MTIP | MIP_STIP | MIP_SSIP); + + // Delegate supervisor timer and other interrupts + // to supervisor mode. + set_csr(mideleg, MIP_STIP | MIP_SSIP); set_csr(medeleg, delegate); -- cgit v1.2.3