From cc5be8b72ba5b072030fdd1d382d7156da43114f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Tue, 26 Jul 2016 01:54:34 +0200 Subject: arch/riscv: Add include/arch/barrier.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit mb() is used in src/arch/riscv/ and src/mainboard/emulation/*-riscv/. It is currently provided by atomic.h, but I think it fits better into barrier.h. The "fence" instruction represents a full memory fence, as opposed to variants such as "fence r, rw" which represent a partial fence. An operating system might want to use precisely the right fence, but coreboot doesn't need this level of performance at the cost of simplicity. Change-Id: I8d33ef32ad31e8fda38f6a5183210e7bd6c65815 Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/15830 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/arch/riscv/virtual_memory.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/arch/riscv/virtual_memory.c') diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index cda9057939..f0cd5f656a 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -14,11 +14,12 @@ * GNU General Public License for more details. */ -#include +#include #include #include -#include #include +#include +#include pte_t* root_page_table; -- cgit v1.2.3