From d9653e1328f8ec07bc1e1fc082f404130c2eee77 Mon Sep 17 00:00:00 2001 From: Thaminda Edirisooriya Date: Thu, 10 Sep 2015 10:55:17 -0700 Subject: riscv-trap-handling: Add functionality, prevent stack corruption Trap handling code was bugged in that it loaded in the wrong stack pointer, overwriting the space the processor uses to talk to its host for doing device requests. Fix this issue, as well as add support for handling misaligned loads the same way we handle misaligned stores. Change-Id: I68ba3a114b7167b3212bb0bed181a7595f0b97d8 Signed-off-by: Thaminda Edirisooriya Reviewed-on: http://review.coreboot.org/11620 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/arch/riscv/trap_util.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/arch/riscv/trap_util.S') diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 9701aaf1f6..274dca6960 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -112,7 +112,7 @@ supervisor_trap_entry: csrw mscratch, sp # load in the top of the machine stack - la sp, 0x80FFF0 + la sp, 0x80FFF0 - 64 1:addi sp,sp,-320 save_tf move a0,sp -- cgit v1.2.3