From 6f3a53b6f61126f05db950e1c0a2c0b4f1552e5f Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Sun, 15 Jan 2017 17:40:51 +0100 Subject: riscv: get SBI calls to work MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SBI calls, as it turned out, were never right. They did not set the stack correctly on traps. They were not correctly setting the MIP instead of the SIP (although this was not really well documented). On Harvey, we were trying to avoid using them, and due to a bug in SPIKE, our avoidance worked. Once SPIKE was fixed, our avoidance broke. This set of changes is tested and working with Harvey which, for the first time, is making SBI calls. It's not pretty and we're going to want to rework trap_util.S in coming days. Change-Id: Ibef530adcc58d33e2c44ff758e0b7d2acbdc5e99 Signed-off-by: Ronald G. Minnich Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/18097 Tested-by: build bot (Jenkins) --- src/arch/riscv/trap_util.S | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'src/arch/riscv/trap_util.S') diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 33579590dc..ae32379562 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -15,6 +15,8 @@ */ #include +#include + .macro restore_regs # restore x registers LOAD x1,1*REGBYTES(a0) @@ -100,16 +102,17 @@ # get faulting insn, if it wasn't a fetch-related trap li x5,-1 STORE x5,36*REGBYTES(x2) -1: + .endm +.globl estack .text .global supervisor_trap_entry supervisor_trap_entry: csrw mscratch, sp # load in the top of the machine stack - li sp, 0x80FFF0 - 64 - 1:addi sp,sp,-320 + la sp, _estack + addi sp,sp,-MENTRY_FRAME_SIZE save_tf move a0,sp jal trap_handler @@ -127,7 +130,8 @@ trap_entry: # TODO: Use the old stack pointer (plus an offset) for exceptions in machine # mode, to avoid overwriting stack data. - li sp, 0x8000fff0 + la sp, _estack + addi sp,sp,-MENTRY_FRAME_SIZE save_tf move a0,sp -- cgit v1.2.3