From 5a01d6a152d705ded302e92c4438d8b8dc495465 Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Sat, 23 Sep 2017 21:39:06 +0200 Subject: arch/riscv: trap handler: Print load/store access width in bits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is easier to read than the raw shift amount that's extracted from load/store instructions. Change-Id: Ia16ab9fbaf55345b654ea65e65267ed900eb29e1 Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/21654 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/arch/riscv/trap_handler.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/arch/riscv/trap_handler.c') diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index ca4954f796..4359ed9974 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -245,7 +245,7 @@ void handle_misaligned_load(trapframe *tf) { insn_t memWidth = (faultingInstruction & widthMask) >> 12; insn_t destMask = 0xF80; insn_t destRegister = (faultingInstruction & destMask) >> 7; - printk(BIOS_DEBUG, "Width: 0x%x\n", memWidth); + printk(BIOS_DEBUG, "Width: %d bits\n", (1 << memWidth) * 8); if (memWidth == 3) { // load double, handle the issue void* badAddress = (void*) tf->badvaddr; @@ -274,7 +274,7 @@ void handle_misaligned_store(trapframe *tf) { insn_t memWidth = (faultingInstruction & widthMask) >> 12; insn_t srcMask = 0x1F00000; insn_t srcRegister = (faultingInstruction & srcMask) >> 20; - printk(BIOS_DEBUG, "Width: 0x%x\n", memWidth); + printk(BIOS_DEBUG, "Width: %d bits\n", (1 << memWidth) * 8); if (memWidth == 3) { // store double, handle the issue void* badAddress = (void*) tf->badvaddr; -- cgit v1.2.3