From 22e0c560bb565642d52e4e0f8bab000c8d06f0b8 Mon Sep 17 00:00:00 2001 From: Xiang Wang Date: Wed, 15 Aug 2018 16:27:05 +0800 Subject: riscv: add support for supervisor binary interface (SBI) SBI is runtime service for OS. For an introduction, please refer to https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md Change-Id: Ib6c1f21d2f085f02208305dc4e3a0f970d400c27 Signed-off-by: Xiang Wang Reviewed-on: https://review.coreboot.org/28096 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/arch/riscv/trap_handler.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) (limited to 'src/arch/riscv/trap_handler.c') diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 8029218fb2..73c52787ae 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -19,6 +19,8 @@ #include #include #include +#include +#include static const char *const exception_names[] = { "Instruction address misaligned", @@ -91,6 +93,20 @@ static void interrupt_handler(trapframe *tf) clear_csr(mie, MIP_MTIP); set_csr(mip, MIP_STIP); + break; + case IRQ_M_SOFT: + if (HLS()->ipi_pending & IPI_SOFT) { + set_csr(mip, MIP_SSIP); + } else if (HLS()->ipi_pending & IPI_FENCE_I) { + asm volatile("fence.i"); + } else if (HLS()->ipi_pending & IPI_SFENCE_VMA) { + asm volatile("sfence.vma"); + } else if (HLS()->ipi_pending & IPI_SFENCE_VMA_ASID) { + asm volatile("sfence.vma"); + } else if (HLS()->ipi_pending & IPI_SHUTDOWN) { + while (HLS()->ipi_pending & IPI_SHUTDOWN) + asm volatile("wfi"); + } break; default: printk(BIOS_EMERG, "======================================\n"); @@ -117,11 +133,13 @@ void trap_handler(trapframe *tf) case CAUSE_LOAD_ACCESS: case CAUSE_STORE_ACCESS: case CAUSE_USER_ECALL: - case CAUSE_SUPERVISOR_ECALL: case CAUSE_HYPERVISOR_ECALL: case CAUSE_MACHINE_ECALL: print_trap_information(tf); break; + case CAUSE_SUPERVISOR_ECALL: + handle_sbi(tf); + return; case CAUSE_MISALIGNED_LOAD: case CAUSE_MISALIGNED_STORE: print_trap_information(tf); -- cgit v1.2.3