From e0e784a456c4d64e5e88ce578371fe6c538db559 Mon Sep 17 00:00:00 2001
From: "Ronald G. Minnich" <rminnich@gmail.com>
Date: Wed, 26 Nov 2014 19:25:47 +0000
Subject: Add UCB RISCV support for architecture, soc, and emulation
 mainboard..

Works in the RISCV version of QEMU.

Note that the lzmadecode is so unclean that it needs a lot of work.
A cleanup is in progress.

We decided in Prague to do this as one thing, because it forms a nice case study
of the bare minimum you need to add to get a new architecture going in qemu.

Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/7584
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
---
 src/arch/riscv/tables.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 96 insertions(+)
 create mode 100644 src/arch/riscv/tables.c

(limited to 'src/arch/riscv/tables.c')

diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c
new file mode 100644
index 0000000000..02659491ea
--- /dev/null
+++ b/src/arch/riscv/tables.c
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ * Copyright (C) 2005 Steve Magnani
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <cpu/cpu.h>
+#include <boot/tables.h>
+#include <boot/coreboot_tables.h>
+#include <string.h>
+#include <cbmem.h>
+#include <lib.h>
+
+#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
+
+#if ! IS_ENABLED(CONFIG_DYNAMIC_CBMEM)
+/*
+ * TODO: "High" tables are a convention used on x86. Maybe we can
+ * clean up that naming at some point.
+ */
+uint64_t high_tables_base = 0;
+uint64_t high_tables_size;
+#endif
+
+void cbmem_arch_init(void)
+{
+}
+
+// WTF. this does not agre with the prototype!
+static struct lb_memory *wtf_write_tables(void)
+{
+	unsigned long table_pointer, new_table_pointer;
+
+#if ! IS_ENABLED(CONFIG_DYNAMIC_CBMEM)
+	if (!high_tables_base) {
+		printk(BIOS_ERR, "ERROR: high_tables_base is not set.\n");
+	}
+
+	printk(BIOS_DEBUG, "high_tables_base: %llx.\n", high_tables_base);
+#endif
+
+	post_code(0x9d);
+
+	table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE,
+						MAX_COREBOOT_TABLE_SIZE);
+	if (!table_pointer) {
+		printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n");
+		return NULL;
+	}
+
+	new_table_pointer = write_coreboot_table(0UL, 0UL,
+				table_pointer, table_pointer);
+
+	if (new_table_pointer > (table_pointer + MAX_COREBOOT_TABLE_SIZE)) {
+		printk(BIOS_ERR, "coreboot table didn't fit (%lx/%x bytes)\n",
+			   new_table_pointer - table_pointer, MAX_COREBOOT_TABLE_SIZE);
+	}
+
+	printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n",
+			new_table_pointer - table_pointer);
+
+	post_code(0x9e);
+
+	/* Print CBMEM sections */
+	cbmem_list();
+
+//	return get_lb_mem();
+	return NULL;
+}
+void write_tables(void)
+{
+	wtf_write_tables();
+}
+
+void cbmem_fail_resume(void)
+{
+}
+void get_cbmem_table(uint64_t *base, uint64_t *size)
+{
+}
-- 
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