From 26f725efc235b282e20aa678f8e683a014920b71 Mon Sep 17 00:00:00 2001 From: Xiang Wang Date: Thu, 11 Oct 2018 17:42:49 +0800 Subject: riscv: add support to block smp in each stage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Each stage performs some basic initialization (stack, HLS etc) and then call smp_pause to enter the single-threaded state. The main work of each stage is executed in a single-threaded state, and the multi-threaded state is restored by call smp_resume while booting the next stage. Change-Id: I8d508c3d0f65a022010e74f8edad7ad2cfdc7dee Signed-off-by: Xiang Wang Reviewed-on: https://review.coreboot.org/29024 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer Reviewed-by: Philipp Hug --- src/arch/riscv/stages.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/arch/riscv/stages.c') diff --git a/src/arch/riscv/stages.c b/src/arch/riscv/stages.c index 80754762bd..4fe040934e 100644 --- a/src/arch/riscv/stages.c +++ b/src/arch/riscv/stages.c @@ -27,10 +27,13 @@ #include #include #include +#include #include void stage_entry(void) { + smp_pause(CONFIG_RISCV_WORKING_HARTID); + /* * Save the FDT pointer before entering ramstage, because mscratch * might be overwritten in the trap handler, and there is code in -- cgit v1.2.3