From a6f9eab44ab0590ca7da33da0b042a8fce8da0f1 Mon Sep 17 00:00:00 2001 From: Xiang Wang Date: Thu, 28 Mar 2019 12:19:30 +0800 Subject: riscv: add support for OpenSBI Call OpenSBI in M-Mode and use it to set up SBI and to lockdown the platform. It will also jump to the specified payload when done. This behaviour is similar to BL31 on aarch31. The payload is 41KiB in size on qemu. Tested on qemu-riscv: Required to boot a kernel as OpenSBI's instruction emulation feature is required on that virtual machine. Tested on SiFive/unleashed: The earlycon is working. No console after regular serial driver should take over, which might be related to kernel config. Change-Id: I2a178595bd2aa2e1f114cbc69e8eadd46955b54d Signed-off-by: Xiang Wang Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/32394 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese --- src/arch/riscv/include/arch/boot.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'src/arch/riscv/include') diff --git a/src/arch/riscv/include/arch/boot.h b/src/arch/riscv/include/arch/boot.h index 34a507edec..c05c669f00 100644 --- a/src/arch/riscv/include/arch/boot.h +++ b/src/arch/riscv/include/arch/boot.h @@ -16,12 +16,17 @@ #ifndef ARCH_RISCV_INCLUDE_ARCH_BOOT_H #define ARCH_RISCV_INCLUDE_ARCH_BOOT_H -#include - #define RISCV_PAYLOAD_MODE_U 0 #define RISCV_PAYLOAD_MODE_S 1 #define RISCV_PAYLOAD_MODE_M 3 +struct prog; void run_payload(struct prog *prog, void *fdt, int payload_mode); +void run_payload_opensbi(struct prog *prog, void *fdt, struct prog *opensbi, int payload_mode); +void run_opensbi(const int hart_id, + const void *opensbi, + const void *fdt, + const void *payload, + const int payload_mode); #endif -- cgit v1.2.3