From 8fad21db54d1435333f832767fb65312db103eb2 Mon Sep 17 00:00:00 2001 From: Thaminda Edirisooriya Date: Wed, 29 Jul 2015 17:43:20 -0700 Subject: riscv-spike: support for Spike emulation of riscv Spike support: QEMU RISCV is broken, and the maintainers at Berkeley are working on it, but at the moment spike is the only way to test on riscv. Add support for spike console output for debugging. Privileged ISA: Update to privileged ISA in RISCV (machine, supervisor, hypervisor, user modes) broke exisitng RISCV asm, and bootblock.S was updated to match the new spec. Clean old assembly [pg: things build with gcc 4.9 now, but don't expect them to work. Hardcoding register names into the assembler language may not be the smartest idea of the RISCV folks.] Change-Id: Ie2c109d3c26712c207512f74f28ce1a925e6e181 Signed-off-by: Thaminda Edirisooriya Reviewed-on: http://review.coreboot.org/11078 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/arch/riscv/bootblock.S | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) (limited to 'src/arch/riscv/bootblock.S') diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 4f2d1ecd55..a26b144458 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -22,30 +22,33 @@ .section ".text._start", "ax", %progbits // Maybe there's a better way. -.space 0x2000 +.space 0x200 .globl _start _start: // pending figuring out this f-ing toolchain. Hardcode what we know works. - la sp, 0x4ef0 // .stacktop -// la a0, trap_entry +// la sp, 0x4ef0 // .stacktop +// la sp, 0x40000 // from src/mainboard/emulation/qemu-riscv + la sp, 0x7FF00 // stack start + stack size + + // make room for HLS + addi sp, sp, -64 // MENTRY_FRAME_SIZE + + + //poison the stack + la t1, 0x40000 + li t0, 0xdeadbeef + sd t0, 0(t1) + // la gp, _gp -// csrw evec, a0 # clear any pending interrupts +#if __GNUC__ < 5 csrwi clear_ipi, 0 +#else + csrwi sip, 0 +#endif - li a0, SR_S | SR_PS | SR_EI | SR_S64 | SR_U64 - or a1, a0, SR_EF | SR_EA - csrw status, a1 - csrr a1, status - csrw status, a0 - -// and a2, a1, SR_EF -// sw a2, have_fp, t0 - -// and a2, a1, SR_EA -// sw a2, have_accelerator, t0 call main .=0x4000 .stack: -- cgit v1.2.3