From 26f725efc235b282e20aa678f8e683a014920b71 Mon Sep 17 00:00:00 2001 From: Xiang Wang Date: Thu, 11 Oct 2018 17:42:49 +0800 Subject: riscv: add support to block smp in each stage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Each stage performs some basic initialization (stack, HLS etc) and then call smp_pause to enter the single-threaded state. The main work of each stage is executed in a single-threaded state, and the multi-threaded state is restored by call smp_resume while booting the next stage. Change-Id: I8d508c3d0f65a022010e74f8edad7ad2cfdc7dee Signed-off-by: Xiang Wang Reviewed-on: https://review.coreboot.org/29024 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer Reviewed-by: Philipp Hug --- src/arch/riscv/bootblock.S | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) (limited to 'src/arch/riscv/bootblock.S') diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 277c3910c0..7f84215dac 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -24,13 +24,6 @@ .global _estack .globl _start _start: - csrr a0, mhartid - li a3, 0 - beq a0, a3, _hart_zero -_hart_loop: - j _hart_loop -_hart_zero: - # The boot ROM may pass the following arguments to coreboot: # a0: the value of mhartid # a1: a pointer to the flattened devicetree @@ -59,6 +52,9 @@ _hart_zero: csrr a0, mhartid call hls_init + li a0, CONFIG_RISCV_WORKING_HARTID + call smp_pause + # initialize entry of interrupt/exception la t0, trap_entry csrw mtvec, t0 -- cgit v1.2.3