From 26f725efc235b282e20aa678f8e683a014920b71 Mon Sep 17 00:00:00 2001 From: Xiang Wang Date: Thu, 11 Oct 2018 17:42:49 +0800 Subject: riscv: add support to block smp in each stage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Each stage performs some basic initialization (stack, HLS etc) and then call smp_pause to enter the single-threaded state. The main work of each stage is executed in a single-threaded state, and the multi-threaded state is restored by call smp_resume while booting the next stage. Change-Id: I8d508c3d0f65a022010e74f8edad7ad2cfdc7dee Signed-off-by: Xiang Wang Reviewed-on: https://review.coreboot.org/29024 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer Reviewed-by: Philipp Hug --- src/arch/riscv/boot.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'src/arch/riscv/boot.c') diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index e1dc61955b..04fba07234 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -19,6 +19,7 @@ #include #include #include +#include /* * A pointer to the Flattened Device Tree passed to coreboot by the boot ROM. @@ -28,7 +29,7 @@ */ const void *rom_fdt; -void arch_prog_run(struct prog *prog) +static void do_arch_prog_run(struct prog *prog) { void (*doit)(void *) = prog_entry(prog); void riscvpayload(const void *fdt, void *payload); @@ -48,3 +49,8 @@ void arch_prog_run(struct prog *prog) doit(prog_entry_arg(prog)); } + +void arch_prog_run(struct prog *prog) +{ + smp_resume((void (*)(void *))do_arch_prog_run, prog); +} -- cgit v1.2.3