From db1e9ce832c4b8aa5d1355b09e353789756ab86a Mon Sep 17 00:00:00 2001 From: Maximilian Brune Date: Mon, 12 Aug 2024 03:47:41 +0200 Subject: arch/riscv: Remove ram probing Previously RAM probing was necessary for our QEMU-RISCV target in order to find the available amount of memory. Now we get the memory from the devicetree propagated by QEMU, so there is no reason to keep it anymore. Tested: Start QEMU-RISCV and cause an exception to make sure the trap handler still works. Signed-off-by: Maximilian Brune Change-Id: I9b1e0dc78fc2a66d6085fe99a71245ff46f8e63c Reviewed-on: https://review.coreboot.org/c/coreboot/+/83873 Reviewed-by: Elyes Haouas Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/arch/riscv/Makefile.mk | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/arch/riscv/Makefile.mk') diff --git a/src/arch/riscv/Makefile.mk b/src/arch/riscv/Makefile.mk index 6754c2202d..c370e3ece1 100644 --- a/src/arch/riscv/Makefile.mk +++ b/src/arch/riscv/Makefile.mk @@ -96,7 +96,6 @@ endif #CONFIG_ARCH_BOOTBLOCK_RISCV ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y) romstage-$(CONFIG_SEPARATE_ROMSTAGE) += romstage.S -romstage-y += ramdetect.c # Build the romstage @@ -120,7 +119,6 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) ramstage-y = ramstage-y += ramstage.S -ramstage-y += ramdetect.c ramstage-y += tables.c ramstage-y += payload.c ramstage-y += fit_payload.c -- cgit v1.2.3