From 2764919dfb78127517dcf13c6ec002f937626b02 Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Tue, 13 Feb 2018 14:01:22 +0100 Subject: arch/riscv: Make RVC support configurable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In order to support RISC-V processors with and without the RVC extension, configure the architecture variant (-march=...) explicitly. NOTE: Spike does support RVC, but currently doesn't select ARCH_RISCV_COMPRESSED, because coreboot's trap handler doesn't support RVC. Change-Id: Id4f69fa6b33604a5aa60fd6f6da8bd966494112f Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/23733 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/arch/riscv/Makefile.inc | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'src/arch/riscv/Makefile.inc') diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index d2b6cce11d..4b2ff035d7 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -15,14 +15,24 @@ ## ################################################################################ -riscv_flags = -I$(src)/arch/riscv/ -mcmodel=medany - -riscv_asm_flags = +################################################################################ +## RISC-V specific options +################################################################################ ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) check-ramstage-overlap-regions += stack endif +riscv_arch = rv64imafd + +ifeq ($(CONFIG_ARCH_RISCV_COMPRESSED),y) + riscv_arch := $(riscv_arch)c +endif + +riscv_flags = -I$(src)/arch/riscv/ -mcmodel=medany -march=$(riscv_arch) + +riscv_asm_flags = -march=$(riscv_arch) + ################################################################################ ## bootblock ################################################################################ -- cgit v1.2.3