From 22e0c560bb565642d52e4e0f8bab000c8d06f0b8 Mon Sep 17 00:00:00 2001 From: Xiang Wang Date: Wed, 15 Aug 2018 16:27:05 +0800 Subject: riscv: add support for supervisor binary interface (SBI) SBI is runtime service for OS. For an introduction, please refer to https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md Change-Id: Ib6c1f21d2f085f02208305dc4e3a0f970d400c27 Signed-off-by: Xiang Wang Reviewed-on: https://review.coreboot.org/28096 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/arch/riscv/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/arch/riscv/Makefile.inc') diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index eacf32acfd..aee4b3b167 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -50,6 +50,7 @@ bootblock-y += trap_util.S bootblock-y += trap_handler.c bootblock-y += fp_asm.S bootblock-y += misaligned.c +bootblock-y += sbi.c bootblock-y += mcall.c bootblock-y += virtual_memory.c bootblock-y += boot.c @@ -118,6 +119,7 @@ ramstage-y += trap_util.S ramstage-y += trap_handler.c ramstage-y += fp_asm.S ramstage-y += misaligned.c +ramstage-y += sbi.c ramstage-y += virtual_memory.c ramstage-y += stages.c ramstage-y += misc.c -- cgit v1.2.3