From 199b75f58a0ffc2ad0871eb4853ca425c78b4893 Mon Sep 17 00:00:00 2001 From: Philipp Hug Date: Thu, 13 Sep 2018 18:11:56 +0200 Subject: arch/riscv: provide a monotonic timer The RISC-V Privileged Architecture specification defines the Machine Time Registers (mtime and mtimecmp) in section 3.1.15. Makes it possible to use the generic udelay. The timer is enabled using RISCV_USE_ARCH_TIMER for the lowrisc, sifive and ucb soc. Change-Id: I5139601226e6f89da69e302a10f2fb56b4b24f38 Signed-off-by: Philipp Hug Reviewed-on: https://review.coreboot.org/27434 Reviewed-by: Ronald G. Minnich Tested-by: build bot (Jenkins) --- src/arch/riscv/Makefile.inc | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/arch/riscv/Makefile.inc') diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index f4b69bb95e..50c1ae69d6 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -56,6 +56,8 @@ bootblock-y += \ $(top)/src/lib/memmove.c \ $(top)/src/lib/memset.c +bootblock-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c + $(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \ @@ -82,6 +84,8 @@ romstage-y += \ $(top)/src/lib/memmove.c \ $(top)/src/lib/memset.c +romstage-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c + # Build the romstage $(objcbfs)/romstage.debug: $$(romstage-objs) @@ -118,6 +122,8 @@ ramstage-y += \ $(top)/src/lib/memmove.c \ $(top)/src/lib/memset.c +ramstage-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c + $(eval $(call create_class_compiler,rmodules,riscv)) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c -- cgit v1.2.3