From 7c9540ea1d46a776ec92b58f99074f51b430f9bb Mon Sep 17 00:00:00 2001
From: Xiang Wang <wxjstz@126.com>
Date: Thu, 11 Oct 2018 17:30:37 +0800
Subject: riscv: add support smp_pause / smp_resume
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See https://doc.coreboot.org/arch/riscv/ we know that we need to execute
smp_pause at the start of each stage and smp_resume at the end of each
stage.

Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/29023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
---
 src/arch/riscv/Kconfig | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'src/arch/riscv/Kconfig')

diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig
index 2d53f422c1..ae83be855b 100644
--- a/src/arch/riscv/Kconfig
+++ b/src/arch/riscv/Kconfig
@@ -32,3 +32,9 @@ config ARCH_RAMSTAGE_RISCV
 config RISCV_USE_ARCH_TIMER
 	bool
 	default n
+
+config RISCV_HART_NUM
+	int
+
+config RISCV_WORKING_HARTID
+	int
-- 
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