From 2764919dfb78127517dcf13c6ec002f937626b02 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Tue, 13 Feb 2018 14:01:22 +0100 Subject: arch/riscv: Make RVC support configurable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In order to support RISC-V processors with and without the RVC extension, configure the architecture variant (-march=...) explicitly. NOTE: Spike does support RVC, but currently doesn't select ARCH_RISCV_COMPRESSED, because coreboot's trap handler doesn't support RVC. Change-Id: Id4f69fa6b33604a5aa60fd6f6da8bd966494112f Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/23733 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/arch/riscv/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/arch/riscv/Kconfig') diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index a30cb7091b..2513c50030 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -2,6 +2,13 @@ config ARCH_RISCV bool default n +config ARCH_RISCV_COMPRESSED + bool + default n + help + Enable this option if your RISC-V processor supports compressed + instructions (RVC). Currently, this enables RVC for all stages. + config ARCH_BOOTBLOCK_RISCV bool default n -- cgit v1.2.3