From 956a8b69d2eaaf597909ff8b5c16b87085eba440 Mon Sep 17 00:00:00 2001 From: Yaroslav Kurlaev Date: Tue, 6 Jul 2021 22:38:37 +0700 Subject: src/mainboard/emulation/qemu-power9: require hb-mode=on MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit "hb-mode" is a -machine flag for QEMU. "hb" stands for Hostboot, which is OpenPower firmware created by IBM. QEMU for PPC64 can run initial program in two different modes: * hb-mode=off with load address 0x00000000 * hb-mode=on with load address 0x08000000 Real hardware always loads firmware at 0x08000000 and coreboot shouldn't require a special build to be run on QEMU. Memory layout is updated to reflect change of load address. Change-Id: I1bdc97a095bd46fccc862985b3bd24f4fa5bc054 Signed-off-by: Yaroslav Kurlaev Signed-off-by: Sergii Dmytruk Reviewed-on: https://review.coreboot.org/c/coreboot/+/57082 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/arch/ppc64/include/arch/io.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/arch/ppc64/include') diff --git a/src/arch/ppc64/include/arch/io.h b/src/arch/ppc64/include/arch/io.h index 6dc0a84b6c..cfaae33f60 100644 --- a/src/arch/ppc64/include/arch/io.h +++ b/src/arch/ppc64/include/arch/io.h @@ -8,7 +8,9 @@ /* Set MSB to 1 to ignore HRMOR */ #define MMIO_GROUP0_CHIP0_LPC_BASE_ADDR 0x8006030000000000 #define LPCHC_IO_SPACE 0xD0010000 +#define FLASH_IO_SPACE 0xFC000000 #define LPC_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_IO_SPACE) +#define FLASH_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + FLASH_IO_SPACE) #define MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR 0x800603FC00000000 /* Enforce In-order Execution of I/O */ -- cgit v1.2.3