From e7a336ac29b1ef5aaa1b0aa4926ed75829b491b1 Mon Sep 17 00:00:00 2001 From: Ionela Voinescu Date: Fri, 24 Jul 2015 15:00:20 +0100 Subject: mips: add coherency argument to identity mapping In order for a U-boot payload to work properly the soc_registers region (device registers) needs to be mapped as uncached. Therefore, add a coherency argument to the identity mapping funcion which will establish the type of mapping. Change-Id: I26fc546378acda4f4f8f4757fbc0adb03ac7db9f Signed-off-by: Ionela Voinescu Reviewed-on: https://review.coreboot.org/12769 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/arch/mips/mmu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/arch/mips/mmu.c') diff --git a/src/arch/mips/mmu.c b/src/arch/mips/mmu.c index 38f496deb3..b144fd3573 100644 --- a/src/arch/mips/mmu.c +++ b/src/arch/mips/mmu.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -70,22 +69,23 @@ static uint32_t pick_pagesize(uint32_t start, uint32_t len) * Identity map the memory from [start,start+len] in the TLB using the * largest suitable page size so as to conserve TLB entries. */ -int identity_map(uint32_t start, size_t len) +int identity_map(uint32_t start, size_t len, uint32_t coherency) { uint32_t pgsize, pfn, entryhi, entrylo0, entrylo1; + coherency &= C0_ENTRYLO_COHERENCY_MASK; while (len > 0) { pgsize = pick_pagesize(start, len); entryhi = start; pfn = start >> 12; - entrylo0 = (pfn << C0_ENTRYLO_PFN_SHIFT) | C0_ENTRYLO_WB | + entrylo0 = (pfn << C0_ENTRYLO_PFN_SHIFT) | coherency | C0_ENTRYLO_D | C0_ENTRYLO_V | C0_ENTRYLO_G; start += pgsize; len -= MIN(len, pgsize); if (len >= pgsize) { pfn = start >> 12; entrylo1 = (pfn << C0_ENTRYLO_PFN_SHIFT) | - C0_ENTRYLO_WB | C0_ENTRYLO_D | C0_ENTRYLO_V | + coherency | C0_ENTRYLO_D | C0_ENTRYLO_V | C0_ENTRYLO_G; start += pgsize; len -= MIN(len, pgsize); -- cgit v1.2.3