From ef4e87b45b96cce65dc26e3bfb67332c3d4d54e1 Mon Sep 17 00:00:00 2001 From: Ionela Voinescu Date: Wed, 18 Feb 2015 13:32:28 +0000 Subject: arch/mips: simplify cache operations Cache operations are simplified by removing assembly implementation and replacing it with simpler C code. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; caches are properly invalidated; BRANCH=none Change-Id: I0f092660549c368e98c208ae0c991fe6f5a428d7 Signed-off-by: Patrick Georgi Original-Commit-Id: bf99849e75813cba865b15af9e110687816e61e4 Original-Change-Id: I965e7929718424f92f3556369d36a18ef67aa0d0 Original-Signed-off-by: Ionela Voinescu Original-Reviewed-on: https://chromium-review.googlesource.com/250792 Original-Reviewed-by: David Hendricks Reviewed-on: http://review.coreboot.org/9820 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/arch/mips/include/arch/cache.h | 4 ---- src/arch/mips/include/arch/cpu.h | 7 +++++++ 2 files changed, 7 insertions(+), 4 deletions(-) (limited to 'src/arch/mips/include') diff --git a/src/arch/mips/include/arch/cache.h b/src/arch/mips/include/arch/cache.h index 907505981b..3b89632dcd 100644 --- a/src/arch/mips/include/arch/cache.h +++ b/src/arch/mips/include/arch/cache.h @@ -23,10 +23,6 @@ #include #include -#define get_icache_line() __get_line_size($16, 1, 19, 3) -#define get_dcache_line() __get_line_size($16, 1, 10, 3) -#define get_L2cache_line() __get_line_size($16, 2, 4, 4) - #define CACHE_TYPE_SHIFT (0) #define CACHE_OP_SHIFT (2) #define CACHE_TYPE_MASK (0x3) diff --git a/src/arch/mips/include/arch/cpu.h b/src/arch/mips/include/arch/cpu.h index 957e427e73..e04621420e 100644 --- a/src/arch/mips/include/arch/cpu.h +++ b/src/arch/mips/include/arch/cpu.h @@ -106,6 +106,13 @@ do { \ #define read_c0_config1() __read_32bit_c0_register($16, 1) #define write_c0_config1(val) __write_32bit_c0_register($16, 1, (val)) +#define read_c0_config2() __read_32bit_c0_register($16, 2) +#define write_c0_config2(val) __write_32bit_c0_register($16, 2, (val)) + +#define read_c0_l23taglo() __read_32bit_c0_register($28, 4) +#define write_c0_l23taglo(val) __write_32bit_c0_register($28, 4, (val)) + + #define C0_ENTRYLO_PFN_SHIFT 6 #define C0_ENTRYLO_WB (0x3 << 3) /* Cacheable, write-back, non-coherent */ #define C0_ENTRYLO_D (0x1 << 2) /* Writeable */ -- cgit v1.2.3