From 7b5f8ef2eab7f1211888ae420d76176f49721601 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 8 Jul 2013 16:22:10 -0600 Subject: arch: Fix spelling Change-Id: Ifea10f0180c0c4b684030a168402a95fadf1a9db Signed-off-by: Martin Roth Reviewed-on: http://review.coreboot.org/3727 Reviewed-by: Ronald G. Minnich Reviewed-by: Paul Menzel Reviewed-by: Stefan Reinauer Tested-by: Stefan Reinauer --- src/arch/armv7/include/armv7.h | 2 +- src/arch/armv7/include/assembler.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/arch/armv7') diff --git a/src/arch/armv7/include/armv7.h b/src/arch/armv7/include/armv7.h index dc111c17ee..147323457a 100644 --- a/src/arch/armv7/include/armv7.h +++ b/src/arch/armv7/include/armv7.h @@ -59,7 +59,7 @@ /* * CP15 Barrier instructions * Please note that we have separate barrier instructions in ARMv7 - * However, we use the CP15 based instructtions because we use + * However, we use the CP15 based instructions because we use * -march=armv5 in U-Boot */ #define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) diff --git a/src/arch/armv7/include/assembler.h b/src/arch/armv7/include/assembler.h index 5e4789b145..7acf0f4a9a 100644 --- a/src/arch/armv7/include/assembler.h +++ b/src/arch/armv7/include/assembler.h @@ -55,6 +55,6 @@ #endif /* - * Cache alligned + * Cache aligned */ #define CALGN(code...) code -- cgit v1.2.3