From 52db0b984523047da19ca3b41558b9dbf45abad7 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Fri, 7 Dec 2012 17:15:04 -0800 Subject: WIP: Initial ARMv7 architecture implementation in coreboot The first ARMv7 CPU we're going to support is the Exynos 5250 used in the Google Snow ChromeBook. Change-Id: I4de8433bbc6202eb8fef2556a11186a3376d411b Signed-off-by: David Hendricks Signed-off-by: Stefan Reinauer Signed-off-by: Ronald G. Minnich Reviewed-on: http://review.coreboot.org/2004 Tested-by: build bot (Jenkins) --- src/arch/armv7/include/cache.h | 56 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 src/arch/armv7/include/cache.h (limited to 'src/arch/armv7/include/cache.h') diff --git a/src/arch/armv7/include/cache.h b/src/arch/armv7/include/cache.h new file mode 100644 index 0000000000..cf8fb5ad61 --- /dev/null +++ b/src/arch/armv7/include/cache.h @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _ASM_CACHE_H +#define _ASM_CACHE_H + +/* + * Invalidate L2 Cache using co-proc instruction + */ +static inline void invalidate_l2_cache(void) +{ + unsigned int val=0; + + asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" + : : "r" (val) : "cc"); + isb(); +} + +void l2_cache_enable(void); +void l2_cache_disable(void); + +/* + * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We + * use that value for aligning DMA buffers unless the board config has specified + * an alternate cache line size. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 64 +#endif + +inline void dram_bank_mmu_setup(unsigned long start, unsigned long size); + +#endif /* _ASM_CACHE_H */ -- cgit v1.2.3