From da3a146caea1e85c9651a7f5889ad2a547d6f5e7 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 13 May 2015 11:19:33 -0700 Subject: arm64: Make SPSR exception masking on EL2 transition explicit The configuration of SPSR bits that mask processor exceptions is kinda oddly hidden as an implict part of the transition() function right now. It would be odd but not impossible for programs to want to be entered with enabled exceptions, so let's move these bits to be explicitly set by the caller like the rest of SPSR instead. Also clear up some macro names. The SPSR[I] bit is currently defined as SPSR_IRQ_ENABLE, which is particularly unfortunate since that bit actually *disables* (masks) interrupts. The fact that there is an additional SPSR_IRQ_MASK definition with the same value but a different purpose doesn't really help. There's rarely a point to have all three of xxx_SHIFT, xxx_MASK and xxx_VALUE macros for single-bit fields, so simplify this to a single definition per bit. (Other macros in lib_helpers.h should probably also be overhauled to conform, but I want to wait and see how many of them really stay relevant after upcoming changes first.) BRANCH=None BUG=None TEST=None Change-Id: Id126f70d365467e43b7f493c341542247e5026d2 Signed-off-by: Patrick Georgi Original-Commit-Id: 715600c83aef9794d1674e8c3b62469bdc57f297 Original-Change-Id: I3edc4ee276feb8610a636ec7b4175706505d58bd Original-Signed-off-by: Julius Werner Original-Reviewed-on: https://chromium-review.googlesource.com/270785 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/10250 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/arch/arm64/transition.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) (limited to 'src/arch/arm64/transition.c') diff --git a/src/arch/arm64/transition.c b/src/arch/arm64/transition.c index 523960e741..8d549ef39f 100644 --- a/src/arch/arm64/transition.c +++ b/src/arch/arm64/transition.c @@ -21,9 +21,6 @@ #include #include -/* Mask out debug exceptions, serror, irq and fiq */ -#define SPSR_MASK (SPSR_FIQ_MASK | SPSR_IRQ_MASK | SPSR_SERROR_MASK | \ - SPSR_DEBUG_MASK) /* Litte-endian, No XN-forced, Instr cache disabled, * Stack alignment disabled, Data and unified cache * disabled, Alignment check disabled, MMU disabled @@ -101,10 +98,6 @@ void transition(struct exc_state *exc_state) hcr_mask = HCR_LOWER_AARCH64; } - /* SPSR: Mask out debug exceptions, serror, irq, fiq */ - elx->spsr |= SPSR_MASK; - raw_write_spsr_current(elx->spsr); - /* SCR: Write to SCR if current EL is EL3 */ if (current_el == EL3) { uint32_t scr = raw_read_scr_el3(); @@ -118,8 +111,9 @@ void transition(struct exc_state *exc_state) raw_write_hcr_el2(hcr); } - /* ELR: Write entry point of program */ + /* ELR/SPSR: Write entry point and processor state of program */ raw_write_elr_current(elx->elr); + raw_write_spsr_current(elx->spsr); /* SCTLR: Initialize EL with selected properties */ sctlr = raw_read_sctlr(elx_el); -- cgit v1.2.3