From 6e41523e70b40c92b05c4d52a2b0ddb276e76921 Mon Sep 17 00:00:00 2001 From: Jimmy Huang Date: Wed, 1 Apr 2015 18:27:12 +0800 Subject: arm64: save and restore cntfrq for secondary cpus CNTFRQ_EL0 can only be set in highest implemented exception level. Save and restore CNTFRQ_EL0 for secondary cpus in coreboot. This patch fix the error below: SANITY CHECK: Unexpected variation in cntfrq. Boot CPU: 0x00000000c65d40, CPU1: 0x00000000000000 BRANCH=none BUG=none TEST=boot to kernel on oak board and check secondary cpu's cntfrq. confirmed cpu1's cntfrq is same as boot cpu's. Change-Id: I9fbc3c82c2544f0b59ec34b1d631dadf4b9d40eb Signed-off-by: Patrick Georgi Original-Commit-Id: b47e4e649efc7f79f016522c7d8a240f98225598 Original-Signed-off-by: Jimmy Huang Original-Change-Id: I2d71b0ccfe42e8a30cd1367d10b0f8993431ef8c Original-Reviewed-on: https://chromium-review.googlesource.com/264914 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/9921 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/arch/arm64/include/arch/startup.h | 3 ++- src/arch/arm64/include/armv8/arch/lib_helpers.h | 12 ++++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) (limited to 'src/arch/arm64/include') diff --git a/src/arch/arm64/include/arch/startup.h b/src/arch/arm64/include/arch/startup.h index bb3a863754..671c13e4cb 100644 --- a/src/arch/arm64/include/arch/startup.h +++ b/src/arch/arm64/include/arch/startup.h @@ -29,8 +29,9 @@ #define TTBR0_INDEX 2 #define SCR_INDEX 3 #define VBAR_INDEX 4 +#define CNTFRQ_INDEX 5 /* IMPORTANT!!! If any new element is added please update NUM_ELEMENTS */ -#define NUM_ELEMENTS 5 +#define NUM_ELEMENTS 6 #ifndef __ASSEMBLY__ diff --git a/src/arch/arm64/include/armv8/arch/lib_helpers.h b/src/arch/arm64/include/armv8/arch/lib_helpers.h index 1e04d48cfa..bb7300f2b7 100644 --- a/src/arch/arm64/include/armv8/arch/lib_helpers.h +++ b/src/arch/arm64/include/armv8/arch/lib_helpers.h @@ -261,6 +261,16 @@ 402: .endm +/* Macro to read from an el0 register */ +.macro read_el0 xreg sysreg + mrs \xreg, \sysreg\()_el0 +.endm + +/* Macro to write to an el0 register */ +.macro write_el0 sysreg xreg temp + msr \sysreg\()_el0, \xreg +.endm + /* Macro to invalidate all stage 1 TLB entries for current EL */ .macro tlbiall_current temp switch_el \temp, 401f, 402f, 403f @@ -547,6 +557,8 @@ uint64_t raw_read_vbar_current(void); void raw_write_vbar_current(uint64_t vbar); uint64_t raw_read_vbar(uint32_t el); void raw_write_vbar(uint64_t vbar, uint32_t el); +uint32_t raw_read_cntfrq_el0(void); +void raw_write_cntfrq_el0(uint32_t cntfrq_el0); /* Cache maintenance system instructions */ void dccisw(uint64_t cisw); -- cgit v1.2.3