From 1c6512962aeaf07dfcb200231cc73bcc64859c7f Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 27 Aug 2014 12:50:26 -0500 Subject: arm64: refactor stage entry Provide a common entry point arm64 cores coming out of reset. Also, take into account CONFIG_ARM64_CPUS_START_IN_ELx to set the correct SCTLR_ELx register. The SCR_EL3 initialization was removed as that can be done in policy code in C later. Part of this refactor allows for greater code reuse for the secure monitor. BUG=chrome-os-partner:31545 BRANCH=None TEST=built and booted to linux on ryu Change-Id: I429f8fd0cdae78318ac171722fa1377924665401 Signed-off-by: Patrick Georgi Original-Commit-Id: f92a5a01f07bc370735d75d695aedd8e2ab25608 Original-Change-Id: If16b3f979923ec8add59854db6bad4aaed35e3aa Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/214668 Original-Reviewed-by: Furquan Shaikh Reviewed-on: http://review.coreboot.org/9012 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/arch/arm64/include/arch/asm.h | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'src/arch/arm64/include') diff --git a/src/arch/arm64/include/arch/asm.h b/src/arch/arm64/include/arch/asm.h index 7760bad850..96c9d13957 100644 --- a/src/arch/arm64/include/arch/asm.h +++ b/src/arch/arm64/include/arch/asm.h @@ -20,19 +20,25 @@ #ifndef __ARM_ARM64_ASM_H #define __ARM_ARM64_ASM_H -#define ALIGN .align 0 - #define ENDPROC(name) \ .type name, %function; \ END(name) -#define ENTRY(name) \ +#define ENTRY_WITH_ALIGN(name, bits) \ .section .text.name, "ax", %progbits; \ .global name; \ - ALIGN; \ + .align bits; \ name: +#define ENTRY(name) ENTRY_WITH_ALIGN(name, 0) + #define END(name) \ .size name, .-name +/* + * Certain SoCs have an alignment requiremnt for the CPU reset vector. + * Align to a 64 byte typical cacheline for now. + */ +#define CPU_RESET_ENTRY(name) ENTRY_WITH_ALIGN(name, 6) + #endif /* __ARM_ARM64_ASM_H */ -- cgit v1.2.3