From 5add43574dc10b9df3b8d050ce9ef14540e339a8 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 17 Sep 2014 11:43:20 -0500 Subject: arm64: add spin table support There was a hacky and one-off spin table support in tegra132. Make this support generic for all arm64 chips. BUG=chrome-os-partner:32082 BRANCH=None TEST=Ran with and without secure monitor booting smp into the kernel. Change-Id: I3425ab0c30983d4c74d0aa465dda38bb2c91c83b Signed-off-by: Patrick Georgi Original-Commit-Id: 024dc3f3e5262433a56ed14934db837b5feb1748 Original-Change-Id: If12083a9afc3b2be663d36cfeed10f9b74bae3c8 Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/218654 Original-Reviewed-by: Furquan Shaikh Reviewed-on: http://review.coreboot.org/9084 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/arch/arm64/armv8/secmon_loader.c | 69 +++++++++++++++++++++++++++--------- 1 file changed, 53 insertions(+), 16 deletions(-) (limited to 'src/arch/arm64/armv8') diff --git a/src/arch/arm64/armv8/secmon_loader.c b/src/arch/arm64/armv8/secmon_loader.c index 066f1c18a8..4d83764234 100644 --- a/src/arch/arm64/armv8/secmon_loader.c +++ b/src/arch/arm64/armv8/secmon_loader.c @@ -24,6 +24,7 @@ #include #include +#include #include #include #include @@ -75,10 +76,43 @@ static secmon_entry_t secmon_load_rmodule(void) return rmodule_entry(&secmon_mod); } -void secmon_run(void (*entry)(void *), void *cb_tables) +struct secmon_runit { + secmon_entry_t entry; + struct secmon_params bsp_params; + struct secmon_params secondary_params; +}; + +static void secmon_start(void *arg) { - struct secmon_params params; uint32_t scr; + struct secmon_params *p = NULL; + struct secmon_runit *r = arg; + + if (cpu_is_bsp()) + p = &r->bsp_params; + else if (r->secondary_params.entry != NULL) + p = &r->secondary_params; + + printk(BIOS_DEBUG, "CPU%x entering secure monitor.\n", cpu_info()->id); + + /* We want to enforce the following policies: + * NS bit is set for lower EL + */ + scr = raw_read_scr_el3(); + scr |= SCR_NS; + raw_write_scr_el3(scr); + + r->entry(p); +} + +void secmon_run(void (*entry)(void *), void *cb_tables) +{ + const struct spintable_attributes *spin_attrs; + static struct secmon_runit runit; + struct cpu_action action = { + .run = secmon_start, + .arg = &runit, + }; printk(BIOS_SPEW, "payload jump @ %p\n", entry); @@ -87,25 +121,28 @@ void secmon_run(void (*entry)(void *), void *cb_tables) return; } - secmon_entry_t doit = secmon_load_rmodule(); + runit.entry = secmon_load_rmodule(); - if (doit == NULL) + if (runit.entry == NULL) die("ARM64 Error: secmon load error"); printk(BIOS_DEBUG, "ARM64: Loaded the el3 monitor...jumping to %p\n", - doit); + runit.entry); - params.entry = entry; - params.arg = cb_tables; - params.elx_el = EL2; - params.elx_mode = SPSR_USE_L; + runit.bsp_params.entry = entry; + runit.bsp_params.arg = cb_tables; + runit.bsp_params.elx_el = EL2; + runit.bsp_params.elx_mode = SPSR_USE_L; + runit.secondary_params.elx_el = EL2; + runit.secondary_params.elx_mode = SPSR_USE_L; - /* We want to enforce the following policies: - * NS bit is set for lower EL - */ - scr = raw_read_scr_el3(); - scr |= SCR_NS; - raw_write_scr_el3(scr); + spin_attrs = spintable_get_attributes(); + + if (spin_attrs != NULL) { + runit.secondary_params.entry = spin_attrs->entry; + runit.secondary_params.arg = spin_attrs->addr; + } - doit(¶ms); + arch_run_on_all_cpus_but_self_async(&action); + secmon_start(&runit); } -- cgit v1.2.3