From c4301f79691995dfedb56cb3e20adea3ecd8f596 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Tue, 14 Apr 2015 16:03:58 +0800 Subject: arm64: introduce data cache ops by set/way to the level specified This patchs introduces level specific data cache maintenance operations to cache_helpers.S. It's derived form ARM trusted firmware repository. Please reference here. https://github.com/ARM-software/arm-trusted-firmware/blob/master/ lib/aarch64/cache_helpers.S BRANCH=none BUG=none TEST=boot on smaug/foster Change-Id: Ib58a6d6f95eb51ce5d80749ff51d9d389b0d1343 Signed-off-by: Patrick Georgi Original-Commit-Id: b3d1a16bd0089740f1f2257146c771783beece82 Original-Change-Id: Ifcd1dbcd868331107d0d47af73545a3a159fdff6 Original-Signed-off-by: Joseph Lo Original-Reviewed-on: https://chromium-review.googlesource.com/265826 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/9979 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/arch/arm64/armv8/secmon/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/arch/arm64/armv8/secmon') diff --git a/src/arch/arm64/armv8/secmon/Makefile.inc b/src/arch/arm64/armv8/secmon/Makefile.inc index ace00b441e..11dcb9a1a8 100644 --- a/src/arch/arm64/armv8/secmon/Makefile.inc +++ b/src/arch/arm64/armv8/secmon/Makefile.inc @@ -35,6 +35,7 @@ secmon-y += psci.c secmon-y += smc.c secmon-y += trampoline.S secmon-y += ../cache.c +secmon-y += ../cache_helpers.S secmon-y += ../cpu.S secmon-y += ../exception.c secmon-y += ../../cpu.c -- cgit v1.2.3