From dea4597bd4e35d8421b1cf8816a3c9dc045b9b36 Mon Sep 17 00:00:00 2001 From: Jimmy Huang Date: Mon, 13 Apr 2015 20:28:38 +0800 Subject: arch/arm64: update mmu translation table granule size, logic and macros 1. change mmu granule size from 64KB to 4KB 2. correct level 1 translation table creation logic 3. automatically calculate granule size related macros BRANCH=none BUG=none TEST=boot to kernel on oak board Change-Id: I9e99a3017033f6870b1735ac8faabb267c7be0a4 Signed-off-by: Patrick Georgi Original-Commit-Id: 2f18c4d5d9902f2830db82720c5543af270a7e3c Original-Change-Id: Ia27a414ab7578d70b00c36f9c063983397ba7927 Original-Signed-off-by: Jimmy Huang Original-Reviewed-on: https://chromium-review.googlesource.com/265603 Original-Reviewed-by: Aaron Durbin Original-Commit-Queue: Yidi Lin Original-Tested-by: Yidi Lin Reviewed-on: http://review.coreboot.org/10009 Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/arch/arm64/armv8/mmu.c | 33 +++++++++++++++++++++++---------- 1 file changed, 23 insertions(+), 10 deletions(-) (limited to 'src/arch/arm64/armv8/mmu.c') diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c index 84b9935a93..99c97fb51e 100644 --- a/src/arch/arm64/armv8/mmu.c +++ b/src/arch/arm64/armv8/mmu.c @@ -164,20 +164,33 @@ static uint64_t init_xlat_table(uint64_t base_addr, uint64_t attr = get_block_attr(tag); /* L1 table lookup */ - /* If VA has bits more than 41, lookup starts at L1 */ - if (l1_index) { - table = get_next_level_table(&table[l1_index]); - if (!table) - return 0; + /* If VA has bits more than L2 can resolve, lookup starts at L1 + Assumption: we don't need L0 table in coreboot */ + if (BITS_PER_VA > L1_ADDR_SHIFT) { + if ((size >= L1_XLAT_SIZE) && + IS_ALIGNED(base_addr, (1UL << L1_ADDR_SHIFT))) { + /* If block address is aligned and size is greater than + * or equal to size addressed by each L1 entry, we can + * directly store a block desc */ + desc = base_addr | BLOCK_DESC | attr; + table[l1_index] = desc; + /* L2 lookup is not required */ + return L1_XLAT_SIZE; + } else { + table = get_next_level_table(&table[l1_index]); + if (!table) + return 0; + } } /* L2 table lookup */ /* If lookup was performed at L1, L2 table addr is obtained from L1 desc else, lookup starts at ttbr address */ - if (!l3_index && (size >= L2_XLAT_SIZE)) { - /* If block address is aligned and size is greater than or equal - to 512MiB i.e. size addressed by each L2 entry, we can - directly store a block desc */ + if ((size >= L2_XLAT_SIZE) && + IS_ALIGNED(base_addr, (1UL << L2_ADDR_SHIFT))) { + /* If block address is aligned and size is greater than + * or equal to size addressed by each L2 entry, we can + * directly store a block desc */ desc = base_addr | BLOCK_DESC | attr; table[l2_index] = desc; /* L3 lookup is not required */ @@ -279,7 +292,7 @@ void mmu_enable(void) /* Initialize TCR flags */ raw_write_tcr_el3(TCR_TOSZ | TCR_IRGN0_NM_WBWAC | TCR_ORGN0_NM_WBWAC | - TCR_SH0_IS | TCR_TG0_64KB | TCR_PS_64GB | + TCR_SH0_IS | TCR_TG0_4KB | TCR_PS_64GB | TCR_TBI_USED); /* Initialize TTBR */ -- cgit v1.2.3