From 4633dc1887057ac0b27502c6c719b332b46eb352 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 12 Aug 2014 17:40:38 -0500 Subject: arm64: handle non-cacheable normal memory Non-cacheable normal memory is needed when one wants an easy way to have a DMA region. That way all the reads and writes will be picked up by the CPU and the device without any cache management operations. BUG=chrome-os-partner:31293 BRANCH=None TEST=With a bevy of other patches can use a carved out DMA region for talking to USB. Change-Id: I8172f4b7510dee250aa561d040b27af3080764d7 Signed-off-by: Patrick Georgi Original-Commit-Id: a5bc7ab1709edd97d8795aa9687e6a0edf26ffc6 Original-Change-Id: I36b7fc276467fe3e9cec4d602652d6fa8098c133 Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/212160 Original-Reviewed-by: Furquan Shaikh Original-Commit-Queue: Furquan Shaikh Reviewed-on: http://review.coreboot.org/8924 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/arch/arm64/armv8/mmu.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'src/arch/arm64/armv8/mmu.c') diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c index e1f088e102..cba1e4d4eb 100644 --- a/src/arch/arm64/armv8/mmu.c +++ b/src/arch/arm64/armv8/mmu.c @@ -67,8 +67,16 @@ static uint64_t get_block_attr(unsigned long tag) attr = (tag & MA_NS)? BLOCK_NS : 0; attr |= (tag & MA_RO)? BLOCK_AP_RO : BLOCK_AP_RW; attr |= BLOCK_ACCESS; - attr |= (tag & MA_MEM)? (BLOCK_INDEX_MEM_NORMAL << BLOCK_INDEX_SHIFT) : - (BLOCK_INDEX_MEM_DEV_NGNRNE << BLOCK_INDEX_SHIFT); + + if (tag & MA_MEM) { + if (tag & MA_MEM_NC) + attr |= BLOCK_INDEX_MEM_NORMAL_NC << BLOCK_INDEX_SHIFT; + else + attr |= BLOCK_INDEX_MEM_NORMAL << BLOCK_INDEX_SHIFT; + } else { + attr |= BLOCK_INDEX_MEM_DEV_NGNRNE << BLOCK_INDEX_SHIFT; + } + return attr; } -- cgit v1.2.3