From 628b8ed549ce109ab01617d62d74891b07fedf31 Mon Sep 17 00:00:00 2001 From: Yidi Lin Date: Fri, 24 May 2024 12:15:11 +0800 Subject: arch/arm64: Support FEAT_CCIDX ARM SoC supports FEAT_CCIDX after ARMv8.3. The register field description of CCSIDR_EL1 is different when FEAT_CCIDX is implemented. If numsets and associativity from CCSIDR_EL1 are not correct, the system would hang during mmu_disable(). Rather than assuming that FEAT_CCIDX is not implemented, this patch adds a check to dcache_apply_all to use the right register format. Reference: - https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/12770 BUG=b:317015456 TEST=mmu_disable works on the FEAT_CCIDX supported SoC. TEST=manually add mmu_disable to emulation/qemu-aarch64/bootblock.c and verify with the command qemu-system-aarch64 -bios \ ./coreboot-builds/EMULATION_QEMU_AARCH64/coreboot.rom -M \ virt,secure=on,virtualization=on -cpu max -cpu cortex-a710 \ -nographic -m 8192M Change-Id: Ieadd0d9dfb8911039b3d36c9419af4ae04ed814c Signed-off-by: Yidi Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/82635 Reviewed-by: Eric Lai Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Yu-Ping Wu --- src/arch/arm64/armv8/cpu.S | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) (limited to 'src/arch/arm64/armv8/cpu.S') diff --git a/src/arch/arm64/armv8/cpu.S b/src/arch/arm64/armv8/cpu.S index a40ee64536..ff13cf6e79 100644 --- a/src/arch/arm64/armv8/cpu.S +++ b/src/arch/arm64/armv8/cpu.S @@ -16,6 +16,9 @@ mov w10, #0 // w10 = 2 * cache level mov w8, #1 // w8 = constant 0b1 + mrs x12, id_aa64mmfr2_el1 // read ID_AA64MMFR2_EL1 + ubfx x12, x12, #20, #4 // [23:20] - CCIDX support + 1: //next_level add w2, w10, w10, lsr #1 // calculate 3 * cache level lsr w1, w0, w2 // extract 3-bit cache type for this level @@ -27,8 +30,14 @@ mrs x1, ccsidr_el1 // w1 = read ccsidr and w2, w1, #7 // w2 = log2(linelen_bytes) - 4 add w2, w2, #4 // w2 = log2(linelen_bytes) - ubfx w4, w1, #3, #10 // w4 = associativity - 1 (also - // max way number) + + cbz x12, 11f // check FEAT_CCIDX for associativity + // branch to 11 if FEAT_CCIDX is not implemented + ubfx x4, x1, #3, #21 // x4 = associativity CCSIDR_EL1[23:3] + b 12f +11: + ubfx x4, x1, #3, #10 // x4 = associativity CCSIDR_EL1[12:3] +12: clz w5, w4 // w5 = 32 - log2(ways) // (bit position of way in DC) lsl w9, w4, w5 // w9 = max way number @@ -36,7 +45,13 @@ lsl w16, w8, w5 // w16 = amount to decrement (way // number per iteration) 2: //next_way - ubfx w7, w1, #13, #15 // w7 = max set #, right aligned + cbz x12, 21f // check FEAT_CCIDX for numsets + // branch to 21 if FEAT_CCIDX is not implemented + ubfx x7, x1, #32, #24 // x7(w7) = numsets CCSIDR_EL1[55:32] + b 22f +21: + ubfx w7, w1, #13, #15 // w7 = numsets CCSIDR_EL1[27:13] +22: lsl w7, w7, w2 // w7 = max set #, DC aligned lsl w17, w8, w2 // w17 = amount to decrement (set // number per iteration) -- cgit v1.2.3