From 3139c8dc05a363810b4dd9c45f01667760e22a58 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sun, 28 Jun 2020 16:33:33 +0300 Subject: ACPI: Drop redundant CBMEM_ID_ACPI_GNVS allocations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Allocation now happens prior to device enumeration. The step cbmem_add() is a no-op here, if reached for some boards. The memset() here is also redundant and becomes harmful with followup works, as it would wipe out the CBMEM console and ChromeOS related fields without them being set again. Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/48701 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/acpi/Kconfig | 6 ++++++ src/acpi/Makefile.inc | 1 + src/acpi/gnvs.c | 7 +------ src/acpi/nvs.c | 23 +++++++++++++++++++++++ 4 files changed, 31 insertions(+), 6 deletions(-) create mode 100644 src/acpi/nvs.c (limited to 'src/acpi') diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig index 11ef12a347..293c194538 100644 --- a/src/acpi/Kconfig +++ b/src/acpi/Kconfig @@ -24,6 +24,12 @@ config ACPI_INTEL_HARDWARE_SLEEP_VALUES Provide common definitions for Intel hardware PM1_CNT register sleep values. +config ACPI_SOC_NVS + bool + help + Set to indicate exists for the platform with a definition + for global_nvs. + config ACPI_NO_PCAT_8259 bool help diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc index 2f06be1a2c..1cd837dd88 100644 --- a/src/acpi/Makefile.inc +++ b/src/acpi/Makefile.inc @@ -12,6 +12,7 @@ ramstage-y += acpigen_usb.c ramstage-y += device.c ramstage-$(CONFIG_CHROMEOS) += chromeos-gnvs.c ramstage-y += gnvs.c +ramstage-$(CONFIG_ACPI_SOC_NVS) += nvs.c ramstage-y += pld.c ramstage-y += sata.c ramstage-y += soundwire.c diff --git a/src/acpi/gnvs.c b/src/acpi/gnvs.c index c0a58f3ba7..aed66f946c 100644 --- a/src/acpi/gnvs.c +++ b/src/acpi/gnvs.c @@ -29,12 +29,7 @@ static void gnvs_assign_cbmc(void) *gnvs_cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); } -/* Platforms that implement GNVS will need to implement these. */ -__weak size_t gnvs_size_of_array(void) -{ - return 0; -} - +/* Needs implementation in platform code. */ __weak uint32_t *gnvs_cbmc_ptr(struct global_nvs *gnvs_) { return NULL; diff --git a/src/acpi/nvs.c b/src/acpi/nvs.c new file mode 100644 index 0000000000..063819158c --- /dev/null +++ b/src/acpi/nvs.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +size_t gnvs_size_of_array(void) +{ + return sizeof(struct global_nvs); +} + +uint32_t *gnvs_cbmc_ptr(struct global_nvs *gnvs) +{ + return &gnvs->cbmc; +} + +/* Some have no chromeos entry. */ +#if CONFIG(MAINBOARD_HAS_CHROMEOS) +void *gnvs_chromeos_ptr(struct global_nvs *gnvs) +{ + return &gnvs->chromeos; +} +#endif -- cgit v1.2.3