From f53214677caca8077d83fbde3d351a2899cdae16 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Thu, 24 Feb 2022 23:03:40 -0700 Subject: util/spd_tools: Encode SDRAM min cycle time (TCKMinPs) ADL encodes CK cycle time as tCKMin whereas Sabrina encodes WCK cycle time. Encode tCKMin as per the respective advisories. BUG=None TEST=Generate the SPD and ensure that tCKMin is encoded accordingly. Minimum CAS Latency time is also impacted and is encoded accordingly. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I99ada7ead3a75befb0f934af871eecc060adcb26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62387 Tested-by: build bot (Jenkins) Reviewed-by: Reka Norman --- spd/lp5/set-1/spd-2.hex | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'spd/lp5/set-1/spd-2.hex') diff --git a/spd/lp5/set-1/spd-2.hex b/spd/lp5/set-1/spd-2.hex index 33da5d70be..69a5fb54f2 100644 --- a/spd/lp5/set-1/spd-2.hex +++ b/spd/lp5/set-1/spd-2.hex @@ -1,11 +1,11 @@ 23 11 13 0E 85 19 B5 18 00 40 00 00 0A 02 00 00 -00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0 +00 00 03 00 00 00 00 00 2B 00 90 A8 90 90 06 C0 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 B9 00 C1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- cgit v1.2.3