From 7ab46f8085146db57699001462da871f2e4d9965 Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Wed, 18 Feb 2015 16:41:26 -0800 Subject: libpayload: add timer driver for cygnus BUG=chrome-os-partner:36011 BRANCH=broadcom-firmware TEST=measured 10 seconds in depthcharge: Starting depthcharge on purin... dpch: time 10 9 8 7 6 5 4 3 2 1 0 Change-Id: I0bcb01c255b19518bb8440111ac81f056c07ed69 Signed-off-by: Patrick Georgi Original-Commit-Id: f5993bd400dd5d38e62d07bc8ce3513175e0d518 Original-Signed-off-by: Daisuke Nojiri Original-Reviewed-on: https://chrome-internal-review.googlesource.com/200569 Original-Reviewed-by: Julius Werner Original-Commit-Queue: Daisuke Nojiri Original-Tested-by: Daisuke Nojiri Original-Change-Id: Id83aae29cec6320d897e0b231d023a9ee885903e Original-Reviewed-on: https://chromium-review.googlesource.com/256415 Reviewed-on: http://review.coreboot.org/9850 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- payloads/libpayload/Config.in | 5 +++++ payloads/libpayload/drivers/timer/cygnus.c | 31 ++++++++++++++++++++++++++++-- 2 files changed, 34 insertions(+), 2 deletions(-) (limited to 'payloads') diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index 455d058dcc..40c57dcb06 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -442,6 +442,11 @@ config IPQ806X_TIMER_REG help Address of the register to read a free running timer value. +config IPROC_PERIPH_GLB_TIM_REG_BASE + hex "Cygnus timer base address" + depends on TIMER_CYGNUS + default 0x19020200 + config USB bool "USB Support" default n diff --git a/payloads/libpayload/drivers/timer/cygnus.c b/payloads/libpayload/drivers/timer/cygnus.c index 16035496b9..e627d3e532 100644 --- a/payloads/libpayload/drivers/timer/cygnus.c +++ b/payloads/libpayload/drivers/timer/cygnus.c @@ -18,12 +18,39 @@ */ #include +struct cygnus_timer { + u32 gtim_glob_low; + u32 gtim_glob_hi; + u32 gtim_glob_ctrl; +}; + +static struct cygnus_timer * const timer_ptr = + (void *)CONFIG_LP_IPROC_PERIPH_GLB_TIM_REG_BASE; + uint64_t timer_hz(void) { - return 0; + /* + * this is set up by coreboot as follows: + * + * PERIPH_CLOCK / + * (((TIMER_GLB_TIM_CTRL_PRESC & TIMER_GLB_TIM_CTRL_PRESC_MASK)>>8) + 1) + * + * where PERIPH_CLOCK is typically 500000000. + */ + return 500000000; } uint64_t timer_raw_value(void) { - return 0; + uint64_t cur_tick; + uint32_t count_h; + uint32_t count_l; + + do { + count_h = readl(&timer_ptr->gtim_glob_hi); + count_l = readl(&timer_ptr->gtim_glob_low); + cur_tick = readl(&timer_ptr->gtim_glob_hi); + } while (cur_tick != count_h); + + return (cur_tick << 32) + count_l; } -- cgit v1.2.3