From ea6b6acd01708ad88f4c6fefc4fd074790245f48 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 9 Jul 2024 23:00:50 +0530 Subject: soc/intel/cmn/cse: Refactor CBMEM ID handling for flexibility This patch refactors the handling of CSE CBMEM IDs to enable platforms to choose whether to perform CSE sync operations within coreboot or defer it to the payload. This separation improves code organization, ensuring `cse_lite.c` focuses on coreboot-specific CSE Lite tasks. Now, platforms can select: * `SOC_INTEL_CSE_LITE_SKU` for CSE sync within coreboot * `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD` for deferred payload sync This change ensures mutually exclusive options, avoiding unnecessary SPI flash size increases. BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: I74f70959715f9fd6d4d298faf310592874cc35d4 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/83393 Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- payloads/libpayload/libc/coreboot.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'payloads/libpayload/libc') diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 7873426473..1d914c5b76 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -262,12 +262,14 @@ static void cb_parse_cbmem_entry(void *ptr, struct sysinfo_t *info) case CBMEM_ID_MEM_CHIP_INFO: info->mem_chip_base = cbmem_entry->address; break; +#if CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD) case CBMEM_ID_CSE_BP_INFO: info->cse_bp_info = cbmem_entry->address; break; case CBMEM_ID_CSE_INFO: info->cse_info = cbmem_entry->address; break; +#endif default: break; } -- cgit v1.2.3