From 6119bea233a29d806ae77b44177feeba7010bfdd Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Fri, 29 Mar 2013 13:24:29 -0700 Subject: armv7: import updated cache/MMU stuff from coreboot This imports the cache/MMU code from coreboot as of 1877cee. Change-Id: I97ec8b9640921a94a4b27d89e4ae6185e9f96f18 Signed-off-by: David Hendricks Reviewed-by: Gabe Black Reviewed-on: https://gerrit.chromium.org/gerrit/48288 Commit-Queue: Stefan Reinauer Tested-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/4134 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- payloads/libpayload/include/armv7/arch/cache.h | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) (limited to 'payloads/libpayload/include/armv7') diff --git a/payloads/libpayload/include/armv7/arch/cache.h b/payloads/libpayload/include/armv7/arch/cache.h index f074a3b158..1db86dc57c 100644 --- a/payloads/libpayload/include/armv7/arch/cache.h +++ b/payloads/libpayload/include/armv7/arch/cache.h @@ -219,10 +219,29 @@ static inline void write_csselr(uint32_t val) isb(); /* ISB to sync the change to CCSIDR */ } +/* read L2 control register (L2CTLR) */ +static inline uint32_t read_l2ctlr(void) +{ + uint32_t val = 0; + asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); + return val; +} + +/* write L2 control register (L2CTLR) */ +static inline void write_l2ctlr(uint32_t val) +{ + /* + * Note: L2CTLR can only be written when the L2 memory system + * is idle, ie before the MMU is enabled. + */ + asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory" ); + isb(); +} + /* read system control register (SCTLR) */ -static inline unsigned int read_sctlr(void) +static inline uint32_t read_sctlr(void) { - unsigned int val; + uint32_t val; asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val)); return val; } -- cgit v1.2.3