From 41e2499734b37d5f38a17416a3512c2c9042e79c Mon Sep 17 00:00:00 2001 From: huang lin Date: Wed, 20 May 2015 17:27:10 +0800 Subject: libpayload: add UDC driver for Designware controller Found in rockchips rk3288 as used in google/veyron. BUG=None TEST=None BRANCH=None Change-Id: I2f2c36c5bea3986a8a37f84c75608b838a8782ae Signed-off-by: Patrick Georgi Original-Commit-Id: 59a0bcd97e8d0f5ce5ac1301910e11b01e2d24b1 Original-Change-Id: Ic89ed54c48d6f9ce125a93caf96471abc6e8cd9d Original-Signed-off-by: Yunzhi Li Original-Reviewed-on: https://chromium-review.googlesource.com/272108 Original-Reviewed-by: Julius Werner Original-Commit-Queue: Lin Huang Original-Tested-by: Lin Huang Reviewed-on: http://review.coreboot.org/10689 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- payloads/libpayload/drivers/udc/dwc2_priv.h | 65 +++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 payloads/libpayload/drivers/udc/dwc2_priv.h (limited to 'payloads/libpayload/drivers/udc/dwc2_priv.h') diff --git a/payloads/libpayload/drivers/udc/dwc2_priv.h b/payloads/libpayload/drivers/udc/dwc2_priv.h new file mode 100644 index 0000000000..8ea4c3a747 --- /dev/null +++ b/payloads/libpayload/drivers/udc/dwc2_priv.h @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Rockchip Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __DWC2_PRIV_H__ +#define __DWC2_PRIV_H__ +#include + +#define EP_MAXLEN (64 * 1024) +#define EP0_MAXLEN 64 + +#define RX_FIFO_SIZE 0x210 +#define DTX_FIFO_SIZE_0_OFFSET RX_FIFO_SIZE +#define DTX_FIFO_SIZE_0 0x10 +#define DTX_FIFO_SIZE_1_OFFSET (DTX_FIFO_SIZE_0_OFFSET +\ + DTX_FIFO_SIZE_0) +#define DTX_FIFO_SIZE_1 0x100 +#define DTX_FIFO_SIZE_2_OFFSET (DTX_FIFO_SIZE_1_OFFSET +\ + DTX_FIFO_SIZE_1) +#define DTX_FIFO_SIZE_2 0x10 + +struct job { + SIMPLEQ_ENTRY(job) queue; // linkage + void *data; + size_t length; + size_t xfered_length; + size_t xfer_length; + int zlp; // append zero length packet? + int autofree; // free after processing? +}; +SIMPLEQ_HEAD(job_queue, job); + +typedef struct dwc2_ep { + dwc2_ep_reg_t *ep_regs; + struct job_queue job_queue; + unsigned txfifo:5; + unsigned busy:1; + unsigned ep_num:8; +} dwc2_ep_t; + +typedef struct dwc2_pdata { + dwc2_reg_t *regs; + dwc2_ep_t eps[MAX_EPS_CHANNELS][2]; + uint32_t fifo_map; + void *setup_buf; +} dwc2_pdata_t; + +#define DWC2_PDATA(ctrl) ((dwc2_pdata_t *)((ctrl)->pdata)) + +#endif -- cgit v1.2.3