From a67dd9de7708563df5b7f019b3c32ac005d5db2e Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Mon, 24 Jul 2017 17:09:35 +0200 Subject: libpayload/storage: Enable bus mastering for AHCI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is (thankfully) not done by coreboot any more for recent chipsets. Change-Id: If56e38037f7b1e53871ee63e6ff297028c59d493 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/20763 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi Reviewed-by: Kyösti Mälkki --- payloads/libpayload/drivers/storage/ahci.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'payloads/libpayload/drivers/storage') diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c index 0e7fd7d8e0..3a0b99df42 100644 --- a/payloads/libpayload/drivers/storage/ahci.c +++ b/payloads/libpayload/drivers/storage/ahci.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include @@ -267,6 +268,10 @@ static void ahci_init_pci(pcidev_t dev) /* Set AHCI access mode. */ ctrl->global_ctrl |= HBA_CTRL_AHCI_EN; + /* Enable bus mastering. */ + const u16 command = pci_read_config16(dev, PCI_COMMAND); + pci_write_config16(dev, PCI_COMMAND, command | PCI_COMMAND_MASTER); + /* Probe for devices. */ for (i = 0; i < 32; ++i) { if (ctrl->ports_impl & (1 << i)) -- cgit v1.2.3