From fc45f0ba9750b8a7d27d7381a66b6204d66adb60 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 31 Mar 2015 22:50:17 -0700 Subject: libpayload: provide icache_invalidate_all() on ARM64 In order to not duplicate the instruction cache invalidation sequence provide a common routine to perform the necessary actions. Also, use it in the appropriate places. BUG=chrome-os-partner:38231 BRANCH=None TEST=Compiles successfully for smaug and boots kernel Change-Id: I1d311dbc70bf225f35d60bb10d8d001065322b3a Signed-off-by: Patrick Georgi Original-Commit-Id: 8ab015156713eb7531378edbd1d779522681d529 Original-Change-Id: I8da7002c56139f8f82503484bfd457a7ec20d083 Original-Signed-off-by: Furquan Shaikh Original-Reviewed-on: https://chromium-review.googlesource.com/263326 Original-Reviewed-by: Aaron Durbin Original-Commit-Queue: Furquan Shaikh Original-Trybot-Ready: Furquan Shaikh Original-Tested-by: Furquan Shaikh Reviewed-on: http://review.coreboot.org/9903 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- payloads/libpayload/arch/arm64/cache.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'payloads/libpayload/arch') diff --git a/payloads/libpayload/arch/arm64/cache.c b/payloads/libpayload/arch/arm64/cache.c index 2ce1cc4a06..799e2d240c 100644 --- a/payloads/libpayload/arch/arm64/cache.c +++ b/payloads/libpayload/arch/arm64/cache.c @@ -120,7 +120,5 @@ void dcache_invalidate_by_mva(void const *addr, size_t len) void cache_sync_instructions(void) { dcache_clean_all(); /* includes trailing DSB (in assembly) */ - iciallu(); /* includes BPIALLU (architecturally) */ - dsb(); - isb(); + icache_invalidate_all(); /* includes leading DSB and trailing ISB */ } -- cgit v1.2.3