From d31cbc74d1317aa5beb8619d93b9337d2c1370de Mon Sep 17 00:00:00 2001 From: Annie Chen Date: Fri, 2 Jun 2023 09:57:28 +0800 Subject: mb/inventec: Add Intel SPR server board Inventec Transformers CPU: - 2 SPR sockets - 64 total PCIe 5.0 lanes with up to 64 lanes of Flex Bus/CXL per CPU - Up to 32 DDR5 DIMM - 1 Gbase-T NIC port - 1 USB3.0 type A, 1 USB2.0 connector - 1 VGA connector BMC: - ASPEED AST2600 BMC - 1 DDR4 8Gb memory - 1 8GB eMMC Test: The board boots to Linux 4.19.6 with all 192 cores available. Change-Id: Ic9d99c3aadaa9f69e6d14d4b1a6c5157f5590684 Signed-off-by: Annie Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/75598 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Wei Chen Reviewed-by: Annie Chen Reviewed-by: Felix Singer Reviewed-by: Angel Pons --- configs/builder/config.transformers | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 configs/builder/config.transformers (limited to 'configs') diff --git a/configs/builder/config.transformers b/configs/builder/config.transformers new file mode 100644 index 0000000000..3903bacc42 --- /dev/null +++ b/configs/builder/config.transformers @@ -0,0 +1,16 @@ +# Inventec Transformers coreboot is modified from Intel ArcherCity CRB +# Inventec Transformers is a dual socket CRB based on Intel. +# Sapphire Rapids Scalable Processor (SPR-SP) chipset. +# +# Type this in coreboot root directory to get a working .config: +# make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.ac + +CONFIG_VENDOR_INVENTEC=y +CONFIG_BOARD_INVENTEC_TRANSFORMERS=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200" +CONFIG_PAYLOAD_LINUX=y +CONFIG_PAYLOAD_FILE="site-local/transformers/linuxboot_bzImage" +CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-55-04" -- cgit v1.2.3