From 94b64431f3de19c79e7494d9ff25f9ebd1ab7cbc Mon Sep 17 00:00:00 2001 From: Mariusz Szafranski Date: Tue, 26 Sep 2017 12:21:13 +0200 Subject: configs: Add intel/harcuvar FSP 2.0 sample configuration Add Intel Harcuvar CRB FSP 2.0 sample configuration. Change-Id: I60ec6921eca17a910cd1b9f8b0b86a1a1bf9bbea Signed-off-by: Mariusz Szafranski Reviewed-on: https://review.coreboot.org/21693 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG Reviewed-by: Martin Roth --- configs/config.intel_harcuvar | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 configs/config.intel_harcuvar (limited to 'configs') diff --git a/configs/config.intel_harcuvar b/configs/config.intel_harcuvar new file mode 100644 index 0000000000..5c7de12cc0 --- /dev/null +++ b/configs/config.intel_harcuvar @@ -0,0 +1,18 @@ +CONFIG_COLLECT_TIMESTAMPS=y +CONFIG_VENDOR_INTEL=y +CONFIG_CBFS_SIZE=0x800000 +CONFIG_BOARD_INTEL_HARCUVAR=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_ENABLE_HSUART=y +CONFIG_UART_PCI_ADDR=0x8000d000 + +#Sample settings for Denverton-NS FSP. +#CONFIG_ADD_FSP_BINARIES=y +#CONFIG_FSP_M_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_M.fd" +#CONFIG_FSP_S_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_S.fd" +#CONFIG_FSP_T_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_T.fd" +#CONFIG_FSP_CAR=y + +#Sample settings for microcode definitions. +#CONFIG_CPU_MICROCODE_HEADER_FILES="../intel/cpu/denverton_ns/microcode/microcode_blob.h" +#CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER=y -- cgit v1.2.3