From e7864ceabc2a5b808007688b2b6fb437a154b29a Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Mon, 22 Oct 2018 14:54:48 +0200 Subject: soc/intel/apollolake: Add reset code to postcar stage Also add a test case for that, a config taken from chromiumos with some references to binaries dropped that aren't in our blobs repo (eg audio firmware). Change-Id: I411c0bacefd9345326f26db4909921dddba28237 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/29223 Reviewed-by: Martin Roth Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- configs/config.google_reef_cros | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 configs/config.google_reef_cros (limited to 'configs/config.google_reef_cros') diff --git a/configs/config.google_reef_cros b/configs/config.google_reef_cros new file mode 100644 index 0000000000..82b9b5234e --- /dev/null +++ b/configs/config.google_reef_cros @@ -0,0 +1,15 @@ +CONFIG_USE_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +CONFIG_BOARD_GOOGLE_REEF=y +CONFIG_CHROMEOS=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y +CONFIG_ELOG_GSMI=y +CONFIG_ELOG_BOOT_COUNT=y +CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144 +CONFIG_SPI_FLASH_SMM=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_CMOS_POST=y +CONFIG_CMOS_POST_OFFSET=0x70 +CONFIG_CMOS_POST_EXTRA=y +CONFIG_PAYLOAD_NONE=y -- cgit v1.2.3