From 4f14cd8a39e65811af08296633842289efa42927 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 18 Dec 2019 19:40:48 +0200 Subject: arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If stage cache is enabled, we should not allow S3 resume to load firmware from non-volatile memory. This also adds board reset for failing to load postcar from stage cache. Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- configs/config.google_reef_cros | 1 - 1 file changed, 1 deletion(-) (limited to 'configs/config.google_reef_cros') diff --git a/configs/config.google_reef_cros b/configs/config.google_reef_cros index 82b9b5234e..9bbb3b3f59 100644 --- a/configs/config.google_reef_cros +++ b/configs/config.google_reef_cros @@ -3,7 +3,6 @@ CONFIG_VENDOR_GOOGLE=y CONFIG_BOARD_GOOGLE_REEF=y CONFIG_CHROMEOS=y CONFIG_ADD_FSP_BINARIES=y -CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y CONFIG_ELOG_GSMI=y CONFIG_ELOG_BOOT_COUNT=y CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144 -- cgit v1.2.3