From 4f14cd8a39e65811af08296633842289efa42927 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Wed, 18 Dec 2019 19:40:48 +0200 Subject: arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If stage cache is enabled, we should not allow S3 resume to load firmware from non-volatile memory. This also adds board reset for failing to load postcar from stage cache. Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- configs/config.google_meep_cros | 1 - 1 file changed, 1 deletion(-) (limited to 'configs/config.google_meep_cros') diff --git a/configs/config.google_meep_cros b/configs/config.google_meep_cros index 3963fd4a98..f87b02b5e9 100644 --- a/configs/config.google_meep_cros +++ b/configs/config.google_meep_cros @@ -2,7 +2,6 @@ CONFIG_VENDOR_GOOGLE=y CONFIG_BOARD_GOOGLE_MEEP=y CONFIG_PAYLOAD_NONE=y -CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SMM=y CONFIG_USE_BLOBS=y -- cgit v1.2.3