From 950d48fe6bee3b3d39f4b2e610489f56fc7fd6c7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>
Date: Wed, 12 Oct 2016 00:18:00 +0200
Subject: MAINTAINERS/RISCV: Cover mb/emulation/spike-riscv
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Change-Id: Id5f3f7f25041189d137ef4daa9f63a3b478763bc
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16988
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'MAINTAINERS')

diff --git a/MAINTAINERS b/MAINTAINERS
index 750fcff607..16cdc4be77 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -124,7 +124,7 @@ M:	Ronald Minnich <rminnich@gmail.com>
 S:	Maintained
 F:	src/arch/riscv/
 F:	src/soc/ucb/
-F:	src/mainboard/emulation/qemu-riscv/
+F:	src/mainboard/emulation/*-riscv/
 
 POWER8 ARCHITECTURE
 M:	Ronald Minnich <rminnich@gmail.com>
-- 
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